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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs5541 low-power, low-voltage, 24-bit ? adc features ? analog-to-digital converter - linearity error: 0.0015% fs - rms noise: 2 v two channel differential mux buffered, fully differential analog and voltage reference inputs scalable v ref input: 0.1 v to analog supply absolute accuracy via calibration flexible digital filters - single conversion settling at 13.4 sps or 4 conversion settling at 53.7 sps with simultaneous 50/60 hz rejection - single conversion settling at 64.8 sps or four conversion settling at 260 sps with 16-bit resolution simple 3-wire serial interface - spi tm and microwire tm compatible - schmitt trigger on serial clock (sclk) low power - single +3.0 v supply - 330 a operating; 10 a sleep current description the cs5541 is a 24-bit low-power and low-voltage ? analog-to-digital converter (adc). it is optimized to con- vert analog signals in dc measurement applications, such as temperature and pressure measurement, and various portable devices where low-power consumption is required. to accommodate these applications, the adc integrates analog input and reference buffers for increased input impedance and includes a two-channel multiplexer. ab- solute accuracy is achieved via one-time or continuous calibration modes. the device draws less than 330a. the cs5541 includes two digital filters. the first filter, which achieves simultaneous rejection of 50/60 hz, pro- vides single conversion settling at 13.4 sps throughput or four conversion settling at 53.7 sps throughput. the second filter, which achieves 16-bit performance, pro- vides single conversion settling at 64.8 sps throughput or four conversion settling at 260 sps throughput. low-power, low-voltage operation and an easy-to-con- figure serial interface reduces time-to-market and makes the cs5541 an ideal device for low-cost, power-con- scious dc measurement applications. ordering information CS5541-BS-40 oc - +85 oc 16-pin ssop differential 4th order ? modulator digital filter serial interface calibration register output register input mux clock generator x1 x1 x1 x1 va+ va- vd+ dgnd vref+ vref- osc1 osc2 ain1+ ain1- ain2+ ain2- sdi sdo sclk cs jun ?01 ds500pp1
cs5541 2 ds500pp1 table of contents 1. characteristics and specifications ........................................................................ 4 2. general description ..................................................................................................... 10 2.1 analog input .............................................................................................................. ....... 10 2.1.1 analog input model ............................................................................................. 10 2.2 voltage reference input .................................................................................................. 1 1 2.2.1 voltage reference input model ........................................................................... 11 2.3 power supply arrangements ........................................................................................... 12 2.4 clock generator ........................................................................................................... .... 12 2.5 serial port interface ..................................................................................................... .... 12 2.6 serial port ............................................................................................................... ......... 13 2.7 serial port initialization sequence ................................................................................... 14 2.8 command register quick reference ............................................................................. 15 2.9 performing conversions/calibrations .............................................................................. 16 2.9.1 continuous calibrations and conversions (reduced output rate) ....................... 16 2.9.2 one time calibration followed by continuous conversions ............................... 17 2.9.3 continuous conversions with default calibration coefficients ........................... 17 2.9.4 continuous conversions with existing calibration coefficients .......................... 17 2.9.5 system calibration .............................................................................................. 17 2.9.6 reading conversions .......................................................................................... 17 2.9.7 output coding ..................................................................................................... 18 2.9.8 digital filter ......................................................................................................... 1 8 2.10 sleep and standby modes ............................................................................................. 20 2.11 power-up sequence and initialization ........................................................................... 20 2.12 pcb layout ............................................................................................................... ..... 20 3. pin descriptions .......................................................................................................... .... 22 4. specification definitions ............................................................................................. 24 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ spi is a trademark of motorola inc. microwire is a trademark of national semiconductor corp. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the informa- tion contained in this document is accurate and reliable. however, the information is subject to change without notice and is p r ovided ? as is ? without warranty of any kind (express or implied). no responsib ility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradema rks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed f or use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechan- ical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publicati on may be used as a basis for man- ufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, in c. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisd ictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com.
cs5541 ds500pp1 3 list of figures figure 1. continuous running sclk timing (not to scale) ................................ 9 figure 2. sdi write timing (not to scale) ............................................................ 9 figure 3. sdo read timing (not to scale) .......................................................... 9 figure 4. multiplexer configuration. ................................................................... 10 figure 5. input model for ain+ and ain- pins. ................................................... 10 figure 6. resolution vs. voltage reference ....................................................... 11 figure 7. resolution vs. voltage reference ....................................................... 11 figure 8. input model for vref+ and vref- pins. ............................................ 11 figure 9. cs5541 configured with +3.0 v analog supply. ................................ 12 figure 10. cs5541 register diagram. ............................................................... 13 figure 11. command and data word timing. ................................................... 13 figure 12. self calibration of offset. .................................................................. 16 figure 13. self calibration of gain. .................................................................... 16 figure 14. digital filter 1 response ................................................................... 19 figure 15. filter 2 response (mclk = 32.768 khz) .......................................... 19 list of tables table 1. filter output word rates .............................................................................................. .. 14 table 2. output conversion data register description (24 bits + flags) ...................................... 18 table 3. cs5541 24-bit output coding......................................................................................... 19
cs5541 4 ds500pp1 1. characteristics and specifications analog characteristics (t a = 25 c; va+ = +3 v 5%, va- = 0 v, vd+ = +3.0 v 5%, dgnd = 0 v, vref+ = 2.5 v, vref- = 0 v, mclk = 32.768 khz, owr (output word rate) = 53.7 sps, bipolar mode, input range = 2.5 v differential, vcm=1.25 v.) (see notes 1 and 2.) notes: 1. applies after a one-time self-calibration at any temperature within -40 c ~ +85 c. 2. specifications guaranteed by design, characterization, and/or test. 3. specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. drift over specified temperature range after calibration at power-up at 25 c. 5. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 6. for peak-to-peak noise multiply by 6.6 for all ranges and output rates. 7. rms noise numbers assume continuous calibration mode is not used. in continuous calibration mode the noise increases by a factor of two. * specifications are subject to change without notice. parameter min typ max units accuracy linearity error - 0.0015 0.003 %fs no missing codes 24 - - bits bipolar offset (note 3) - 16 tbd lsb 24 unipolar offset (note 3) - 32 tbd lsb 24 offset drift (notes 3 and 4) - 20 - nv/ c bipolar full scale error - 8 31 ppm unipolar full scale error - 16 62 ppm full scale drift (note 4) - 1 - ppm/ c noise (notes 5, 6, and 7) filter type output word rate (sps) -3 db filter frequency (hz) rms noise (v) single conversion settling with 50/60 hz rejection 13.4 11.96 2 four conversion settling with 50/60 hz rejection 53.7 11.96 2 fast filter with single conversion settling 64.8 56.91 35 fast filter with four conversion settling 260 56.91 35
cs5541 ds500pp1 5 analog characteristics (continued) notes: 8. see section 2.1, ?analog input ? . 9. see section 2.2, ? voltage reference input ? . 10. vref must be less than or equal to supply voltages. 11. the cs5541 includes two digital filters. the first filter, which achieves simultaneous rejection of 50/60 hz, provides single conversion settling at 13.4 sps throughput or four conversion settling at 53.7 sps throughput. the second filter, which achieves 16-bit performance, provides single conversion settling at 64.8 sps throughput or four conversion settling at 260 sps throughput. 12. all outputs unloaded. all digital inputs at cmos levels. parameter min typ max units analog inputs common mode + signal on ain+ or ain- (bipolar/unipolar mode) single supply dual supply 0.0 va- - - va+ va+ v v cvf current on ain+, ain- (note 8) - 12 - na input leakage for mux when off - 10 - pa common mode rejection dc 50, 60hz - - 120 120 - - db db input capacitance - 8 - pf voltage reference inputs range (vref+) - (vref-) (note 10) 0.1 2.5 (va+) - (va-) v cvf current on vref+ and vref- (note 9) - 20 - na common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance - 12 - pf dynamic characteristics modulator sampling frequency - mclk/2 - hz filter settling to 1/2 lsb (full scale step) (note 11) 13.4 sps owr 53.7 sps owr 64.8 sps owr 260 sps owr - - - 1/owr 4/owr 1/owr 4/owr - - - - s s s s power supplies dc power supply currents (normal mode) i a+ i d+ - - 225 25 280 36 a a power consumption normal mode (note 12) standby mode sleep mode - - - 750 75 30 1000 - - w w w power supply rejection dc positive supplies dc negative supply - - 80 80 - - db db
cs5541 6 ds500pp1 3 v digital characteristics (t a = 25 c; va + = 3.0 v 5%, va- = 0 v, vd+ = 3.0 v 5%, dgnd = 0 v.)(see notes 2 and 13.) notes: 13. all measurements performed under static conditions. parameter symbol min typ max units high-level input voltage: all pins except osc1, sclk osc1 sclk v ih v ih v ih 0.6vd+ tbd (vd+)-0.45 - - - - - - v v v low-level input voltage: all pins except osc1, sclk osc1 sclk v il v il v il - - - - - - 0.16vd+ tbd 0.6 v v v high-level output voltage: (sdo pin) i out = -1.0 ma v oh (vd+)-0.25 - - v low-level output voltage: (sdo pin) i out = 1.0 ma v ol --0.2v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf
cs5541 ds500pp1 7 absolute maximum ratings (dgnd = 0 v) (see note 14.) notes: 14. all voltages measured with respect to digital ground (dgnd). 15. va+ and va- must satisfy {(va+) - (va-)} +4.0 v. 16. vd+ and va- must satisfy {(vd+) - (va-)} +4.0 v. 17. applies to all pins including continuous overvoltage conditions at the analog input (ain) pins. 18. transient currents up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 19. total power dissipation, including all input currents and output currents. warning : operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max units dc power supplies (notes 15 and 16) positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 -0.3 - - - +4.0 +4.0 +0.3 v v v input current, any pin except supplies (notes 17 and 18) i in --10ma output current i out --25ma power dissipation (note 19) pdn - - 500 mw analog input voltage ain and vref pins v ina (va-) + (-0.3) - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -40 - +85 c storage temperature t stg -65 - +150 c
cs5541 8 ds500pp1 switching characteristics (t a = 25 c; va+ = +3.0 v 5% va- = 0 v, vd+ = 3.0 v 5%, dgnd = 0 v; input levels: logic 0 = 0 v, logic 1 = vd+; c l = 50 pf) notes: 20. device parameters are specified with 32.768 khz clock; however, clocks up to 40 khz can be used for increased throughput. 21. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 22. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. parameter symbol min typ max units master clock frequency: external clock internal oscillator (note 20) mclk 5 - - 32.768 40 - khz master clock duty cycle 40 - 60 % rise times (note 21) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 21) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 32.768 khz (note 22) t ost -500-ms power-on-reset period t por -490-mclk cycles serial port timing serial clock frequency sclk 0 - 2 mhz serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to sclk rising t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 --150ns sclk falling to new data bit t 8 --150ns cs rising to sdo hi-z t 9 --150ns
cs5541 ds500pp1 9 figure 1. continuous running sclk timing (not to scale) cs sclk t1 t6 t2 t3 figure 2. sdi write timing (not to scale) cs sclk msb msb-1 lsb sdi t3 t6 t4 t5 t1 t2 figure 3. sdo read timing (not to scale) cs sclk msb msb-1 lsb sdo t7 t9 t8 t1 t2
cs5541 10 ds500pp1 2. general description the cs5541 is a 24-bit, low-power and low-volt- age ?? analog-to-digital converter (adc). it is optimized to convert analog signals in dc mea- surement applications such as temperature and pressure measurement, and various portable devic- es where low power consumption is required. to accommodate these applications, the adc inte- grates analog input and reference buffers for in- creased input impedance and includes a two-channel multiplexer. absolute accuracy is achieved via one-time or continuous calibration modes. the device also operates with a variety of supply configurations while drawing less than 330 a. the cs5541 includes two digital filters. the first filter which achieves simultaneous rejection of 50/60 hz provides single conversion settling at 13.4 sps throughput or four conversion settling at 53.7 sps throughput. the second filter which achieves 16-bit performance provides single con- version settling at 64.8 sps throughput or four con- version settling at 260 sps throughput. (either filter ? s output word rates can be increased by using a faster master clock, up to 40 khz). to ease communication between the adcs and a microcontroller, the converters include a simple three-wire serial interface which is spi and mi- crowire compatible. a schmitt trigger input is pro- vided on the serial clock (sclk) input. 2.1 analog input figure 4 illustrates a block diagram of the cs5541. the device consists of a multiplexer, a unity gain coarse/fine charge input buffer, a fourth order ?? modulator, and a digital filter. 2.1.1 analog input model figure 5 illustrates the input models for the ain pins. the model includes a coarse/fine charge buff- er which reduces the dynamic current demand on the analog input signal. the buffer is designed to accommodate rail to rail (common-mode plus sig- nal) input voltages. typical cvf (sampling) cur- rent is about 12 na (mclk = 32.768 khz). application note 30, ? switched-capacitor a/d in- put structures ? , details various input architectures. vref+ sinc digital filter m u x ain2+ ain2- ain1+ ain1- x1 x1 x1 vref- x1 differential 4 order ? modulator th 4 serial port cs sdi sdo sclk figure 4. multiplexer configuration. ain c = 8 pf f = 2*mclk = 65.536 khz coarse 2 fine 1 i n = cv os f v os 25mv figure 5. input model for ain+ and ain- pins.
cs5541 ds500pp1 11 2.2 voltage reference input the differential voltage between vref+ and vref- sets the nominal full scale input range of the converter. for a single-ended reference voltage, the reference output is connected to the vref+ pin of the cs5541 and the ground reference is connect- ed to the vref- pin. note that the differential ref- erence voltage can be from 0.1 v to ((va+)- (va-)). the noise-free resolution of a single sam- ple from the adc is directly proportional to the voltage reference as depicted in figures 6 and 7. note: when a lower reference voltage is used, the resulting code widths are smaller. since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier. 2.2.1 voltage reference input model figure 8 illustrates the input models for the vref pins. it includes a coarse/fine charge buffer which reduces the dynamic current demand on the exter- nal reference. the reference ? s buffer is designed to accommodate rail-to-rail (common-mode plus sig- nal) input voltages. typical cvf (sampling) cur- rent is about 20 na (mclk = 32.768 khz; see figure 8). 14 15 16 17 18 19 20 00.511.522.53 vref (v) noise-free resolution (bits) figure 6. typical noise-free resolution vs. voltage reference one-time cal, 4 cycle settling, 50/60 hz reject noise-free res. = log 2 (bipolar span/6.6*rms noise) 13 14 15 16 17 18 19 0 0.5 1 1.5 2 2.5 3 vref (v) noise-free resolution (bits) figure 7. typical noise-free resolution vs. voltage reference continuous cal, 1cycle settling, 50/60 hz reject noise-free res. = log 2 (bipolar span/6.6*rms noise) vref c = 12 pf f = 2*mclk = 65.536 khz coarse 2 fine 1 i n = cv os f v os 25mv figure 8. input model for vref+ and vref- pins.
cs5541 12 ds500pp1 2.3 power supply arrangements the cs5541 is designed to operate with a total sup- ply voltage of 3.0 v 5%. for maximum flexibility separate pins are provided for va+, va-, vd+, and dgnd, which is especially useful with ground referenced input signals. figure 9 illustrates the cs5541 connected with a single +3.0 v supply for both the analog and digital sections. 2.4 clock generator the cs5541 includes an oscillator circuit which can be connected with an external crystal to pro- vide the master clock for the chip. the chip is de- signed to operate using a low-cost 32.768 khz ? tuning fork ? type crystal. one lead of the crystal should be connected to osc1 and the other to osc2. a 10 megohm resistor should be connected in parallel with the crystal. lead lengths should be minimized to reduce stray capacitance. the con- verter will operate with an external (cmos com- patible) clock applied at osc1 with frequencies up to 40 khz. 2.5 serial port interface the cs5541 ? s serial interface consists of four con- trol lines: cs , sdi, sdo, and sclk. cs , chip select, is the control line which enables access to the serial port. if the cs pin is tied to logic 0, the port will function as a three wire interface. sdi, serial data in, is the data signal used to trans- fer data to the converters. sdo, serial data out, is the data signal used to transfer output data from the converters. the sdo output will be held at high impedance any time cs is at logic 1. sclk, serial clock, is the serial bit-clock which controls the shifting of data to or from the adc ? s serial port. the cs pin must be held at logic 0 be- fore sclk transitions can be recognized by the port logic. to accommodate opto-isolators sclk is designed with a schmitt-trigger input. osc2 vd+ va+ vref+ vref- dgnd ain1+ sclk sdo sdi cs5541 osc1 cs +3.0 v analog 16 15 3 1 11 9 8 7 6 10 5 12 optional clock source serial data interface 5 khz ~ 40 khz ain1- 4 va- 2 0.1 f 0.1 f 10 ? ain2+ ain2- + - voltage reference 14 13 analog signal sources supply 10 m ? figure 9. cs5541 configured with +3.0 v analog supply.
cs5541 ds500pp1 13 2.6 serial port the cs5541 includes a state machine with an 8-bit command register, which instructs the adc to per- form conversions, and a 24-bit conversion data reg- ister (read only) to store conversion results. figure 10 illustrates a block diagram of the internal regis- ters. after power is applied to the adc (the adc in- cludes a power-on reset circuit) or after the user transmits the serial port initialization sequence, the serial port is set to the command mode. the con- verter stays in this mode until a valid 8-bit com- mand is received (the first 8 bits into the serial port). once a valid 8-bit data mode command is re- ceived and interpreted by the adc ? s command register, the serial port enters the data mode and continuous conversions are performed. the sdo pin falls at the end of a conversion and the user may read the conversion data by providing 32 serial clocks (sclks), as shown in figure 11 . the first 8 sclks are needed to clear the sdo flag and to read the status flags. during the next 24 sclks, the conversion data is shifted out of the serial port. to continue performing the conversions, sdi must be kept low during the status read time. a new command can be issued any time other than during the data read. if the command happens to be a pow- er save command, the serial port goes back to the command mode. otherwise, the conversions will stop in progress and start new conversions based on the information in the command byte, and the serial port will remain in the data mode. section 2.8, ? command register quick reference ? , lists all valid commands. 2.7 serial port initialization sequence to initialize the serial port of the adc to the com- mand mode, the user can transmit the serial port initialization sequence. the port initialization se- quence involves clocking seven (or more) sync1 command bytes (0xff) followed by one sync0 command byte (0xfe). note that this sequence places the adc ? s serial port in the command mode where it waits until a valid command is received. this sequence does not reset the internal registers to their default settings. further note that the se- quence can be issued at any time and aids signifi- cantly in initial code development. serial interface cs sdi sdo sclk command register (1 8) write only read only conversion data register (1x24) figure 10. cs5541 register diagram. 1st command time 8 sclks sdo sclk sdi t d * data time 24 sclks msb lsb 0 1 ch od of 1 1 8 sclks to read status sdi set low while reading status & data 1 t o * * t d , t o - refer to table 1. for output timing. figure 11. command and data word timing.
cs5541 14 ds500pp1 2.8 command register quick reference notes: 23. after entering a power save mode, the user must wait a minimum of 2 system clocks before issuing a convert command. 24. a power save mode cannot be entered by selectively setting the d5 bit. 0xax must be written to the command register before the sleep mode will be enabled. similarly, 0xbx must be written to the command register before the standby mode will be enabled. 25. if four cycle settling is selected (d3 = ? 1 ? ), the part will perform a one-time calibration when continuous calibration is chosen. d7(msb)d6d5d4d3d2d1d0 cb ch ps u/b fs1 fs0 c1 c0 bit name value function d7 command bit, cb 0 1 reserved logic 1 for executable commands d6 channel select, ch 0 1 activate ain1 for conversion activate ain2 for conversion d5 power save, ps notes 23, 24 0 1 data mode power save mode (standby or sleep) d4 unipolar/bipolar, u/b 0 1 bipolar conversion mode unipolar conversion mode d3-d2 filter select, fs1-fs0 note 25 00 01 10 11 single cycle settling, 50/60 hz reject single cycle settling, no 50/60 hz reject four cycle settling, 50/60 hz reject four cycle settling, no 50/60 hz reject d1-d0 conversion calibration select, c1-c0 00 01 10 11 calibrate prior to each point perform a one time calibration use default calibration coefficients for conversions use existing calibration coefficients for conversion
cs5541 ds500pp1 15 2.9 performing conversions/calibrations the cs5541 offers four conversion/self-calibration modes (if a user requires system calibration, this can be accommodated in the system microcontrol- ler). the first mode allows the user to calibrate con- tinuously between each conversion. the second mode allows the user to calibrate once after the command is issued and then continuously convert on the channel selected using the calibration result. the third mode allows the user to skip calibration; however, it performs conversions with the default calibration coefficients. the final mode allows the user to use the previous calibration coefficients to perform continuous conversions on the channel se- lected. the sections that follow detail the differenc- es between the conversion modes. the sections also explain how to decode the conversion word into the respective flag and data bits. 2.9.1 continuous calibrations and conver- sions (reduced output rate) this mode performs an offset and gain calibration prior to each conversion. note that the effective throughput in this mode is reduced by two as a cal- ibration is performed prior to each conversion. nevertheless, after the first command instructing the adc to enter this mode is given, an offset cali- bration is performed followed by a gain calibration. then the first data conversion is performed. subse- quent conversions are offset calibration followed by data conversion. then, a gain calibration is per- formed followed by a data conversion. the adc repetitively steps through this sequence until a new command is issued. note: the cs5541 offers self calibration where the adc calibrates out offset and gain errors due to the adc itself. calibration in the cs5541 is used to set the zero and gain slope of the adc ? s transfer function. for the self-calibration of offset, the converter internally ties the inputs of the modulator together and routes them to the vref- pin as shown in figure 12. vref- must be tied to a fixed voltage between va+ and va-. for self-calibration of gain, the differential inputs of the modulator are connected to vref+ and vref- as shown in figure 13. further note that each calibration step (offset or gain) takes one conversion cycle to complete. however, after the adc is reset, it is functional and can perform measurements without being calibrated (see perform continuous conversions with default calibration coefficients section for details). in this case, the converter will utilize the initialized values of the on-chip registers (offset = 0, gain = 1.0) to calculate output words. any initial offset and gain errors in the internal circuitry of the chip will remain. ain+ ain- + - vref- figure 12. self calibration of offset. ain+ ain- + - vref+ vref- + - reference figure 13. self calibration of gain.
cs5541 16 ds500pp1 2.9.2 one time calibration followed by con- tinuous conversions after the first command instructing the adc to en- ter this mode is given, an offset calibration is per- formed followed by a gain calibration. then the first data conversion is performed. subsequent con- versions do not include new calibrations. this al- lows the adc to provide maximum throughput for the filter rate selected. 2.9.3 continuous conversions with default calibration coefficients after the command instructing the adc to enter this mode is given, the adc will utilize the initial- ized values of the on-chip calibration registers (offset = 0, gain = 1.0) for all conversions. this al- lows the adc to provide maximum throughput for the filter rate selected. this mode is recommended when the user is performing a system calibration. 2.9.4 continuous conversions with existing calibration coefficients after the command instructing the adc to enter this mode is given, the adc will use the coeffi- cients from the previous calibration to calculate conversions. if no prior calibration has been per- formed since power-up, the adc will use the de- fault calibration coefficients (offset = 0, gain = 1). the adc performs conversions at the maximum throughput for the filter rate selected. 2.9.5 output word timing table 1 describes the output word timing of the cs5541. d3-d0 are the last four bits of the com- mand word issued, as described in section 2.8. both t d and t o are represented graphically in figure 11. t d represents the amount of time for a conver- sion to be completed, once a valid command is re- ceived. t o is the time required for all subsequent conversions, before a new command is received. ? throughput ? is the rate at which those subsequent conversions are output. notes: 26. t d can be off by one mclk cycle if sclk is asynchronous to mclk. 27. throughput calculations assume that mclk = 32.768 khz. d3-d0 t d - first output (cycles) note 26 t o - subsequent outputs (cycles) throughput (sps) note 27 0000 7358 4884 6.7093 0001 7358 2442 13.418 001x 2474 2442 13.418 0100 1550 1012 32.379 0101 1550 506 64.759 011x 538 506 64.759 100x 7358 610 53.718 101x 2474 610 53.718 110x 1550 126 260.06 111x 538 126 260.06 table 1. filter output word rates
cs5541 ds500pp1 17 2.9.6 system calibration if a system level calibration is to be performed us- ing a system microcontroller, it is best to put the converter in the continuous conversions with de- fault calibration coefficients mode. the user would configure the system with a zero-level input and store the resulting conversion for system offset correction. then the user would configure the sys- tem with a full-scale input level and store the re- sulting conversion for system full-scale correction. correction of converter data is then performed us- ing the system microcontroller. 2.9.7 reading conversions at the completion of a conversion, sdo will fall to logic 0 to indicate that the conversion is complete. if calibration modes are used they will be transpar- ent to user and only affect the effective throughput of the adc. nevertheless, to read a conversion word, the user must issue 8 sclks (sdi = logic 0 for the null command and remain in this mode or sdi can be used to clock in a new command) to clear the sdo flag and read the status flags. upon the falling edge of the 8 th sclk, the sdo pin will present the first bit (msb) of the conversion word. 24 sclks (high, then low) are then required to read the conversion word from the port. upon the falling edge of the 32 nd sclk, sdo will return high, waiting till the next conversion is complete before it falls again. when operating in any of the conversion modes, the user need not read every conversion. if the user chooses not to read a conversion after sdo falls, sdo will rise one mclk clock cycle before the next conversion is completed and then fall to signal that another conversion word is available. to exit the particular conversion mode, the user must issue any valid command, other than the null com- mand, to the sdi input. the new command can be issued anytime other than during the data read. if the user wants to read the last conversion data and issue the new command, the following protocol is required: after sdo falls, read the status flags (keeping sdi low, 8 sclks), followed by the con- version data (24 sclks). then follow it up with the new command at sdi (8 sclks). if the command happens to be a power save com- mand, the serial port goes back to the command mode. otherwise, the conversion will stop in progress and start new conversions based on the in- formation in the command byte, and the serial port remains in the data mode. note: 1) if the user begins to clear the sdo end-of- conversion flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. 2) if a new conversion command is issued to the converter while it is performing a conversion, the filter will stop the current conversion and start a new convolution cycle to perform a new conversion. 3) if a new conversion command is issued when sdo is low, sdo will output 01111, then ch, od, and of. afterwards, sdo will remain high until one mclk cycle before the new data is ready, then fall to indicate that the conversion is completed. 2.9.8 output coding the cs5541 outputs 24-bit data conversion words. to read a conversion word the user must read the conversion data register. the conversion data reg- ister is 24 bits long and outputs the data word msb first. once a conversion is complete, sdo falls and 32 sclk ? s are required to read the results. the first 8 sclks are used to clear the sdo flag and clock out the status flags. the channel indicator (ch) bit keeps track of which input channel was converted. the oscillation detect (od) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. this does not occur under normal oper- ating conditions, but may occur whenever the input to the converter is extremely overranged. if the od bit is set, the conversion data bits can be completely
cs5541 18 ds500pp1 erroneous. the od flag bit will be cleared to logic 0 when the modulator becomes stable. the overrange flag (of) bit is set to a logic 1 any time the input signal is: 1) more positive than posi- tive full scale, 2) more negative than zero (unipolar mode), 3) more negative than negative full scale (bipolar mode). it is cleared back to logic 0 when- ever a conversion word occurs which is not over- ranged. the last 24 sclks are used to clock data out of the conversion data register. table 2 and table 3 illustrate the output coding for the cs5541. unipolar conversions are output in bi- nary format and bipolar conversions are output in two ? s complement format. 2.9.9 digital filter the cs5541 includes two digital filters. the first filter which achieves simultaneous rejection of 50/60 hz provides single conversion settling at 13.4 sps throughput or four conversion settling at 53.7 sps throughput. the second filter which achieves 16-bit performance provides single con- version settling at 64.8 sps throughput or four con- version settling at 260 sps throughput. the first filter (13.4 sps and 53.7 sps throughput) is optimized to yield better than 80 db rejection be- tween 47 hz to 63 hz (i.e. 80 db minimum rejec- tion for both 50 hz and 60 hz) when the master clock is 32.768 khz. the filter has a response as shown in figure 14. the second filter is optimized for higher through- put, and does not provide 50 hz or 60 hz rejection. it has a frequency response that is shown in figure 15. to ease code development, each filter (13.4 sps or 64.8 sps throughput) has a mode that only outputs fully settled output conversions (every 4 th convolu- tion). d31 d30 d29 d28 d27 d26 d25 d24 01 1 1 1 chodof d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 msb 2221201918 17 16 15 14 13 12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 109876 5 4 3 2 1lsb table 2. output conversion data register description (24 bits + flags) note: vfs in the table equals the voltage between ground and full scale for the unipolar mode, or the voltage between full scale for the bipolar mode. see text about error flags under overrange conditions. unipolar input voltage offset binary bipolar input voltage two ? s complement >(vfs-1.5 lsb) ffffff >(vfs-1.5 lsb) 7fffff vfs-1.5 lsb ffffff ----- fffffe vfs-1.5 lsb 7fffff ----- 7ffffe vfs/2-0.5 lsb 800000 ----- 7fffff -0.5 lsb 000000 ----- ffffff +0.5 lsb 000001 ----- 000000 -vfs+0.5 lsb 800001 ----- 800000 <(+0.5 lsb) 000000 <(-vfs+0.5 lsb) 800000 table 3. cs5541 24-bit output coding
cs5541 ds500pp1 19 to accommodate higher throughput requirements, each filter has a mode (53.7 sps or 260 sps throughput) that outputs every single convolution. this allows users to see input signal trends at high- er update rates. note: the converter ? s digital filter characteristics linearly scale with mclk. 2.10 sleep and standby modes the cs5541 accommodates three power consump- tion modes: normal, sleep, and standby. the nor- mal power consumption mode is entered by default after a power-on-reset. in this mode, the cs5541 typically consumes 750 w. the sleep mode is entered whenever the sleep command, 0xax, is issued to the serial port. the adc immediately enters sleep after the command is issued, reducing the consumed power to around 30 w. during sleep, most of the analog portion of the chip is powered down and filter convolutions are halted. to exit sleep (i.e. to return to normal power consumption mode), the user must transmit a data mode command. since the sleep mode dis- ables the oscillator, approximately a 500 ms crystal oscillator start-up delay period is required before the adc returns to the normal power consumption mode. note that if an external clock is used, the adc will return to normal power mode within 3 milliseconds. the standby mode is entered by writing 0xbx to the part. the standby mode performs the same function as the sleep mode except that the oscilla- tor is not powered down. this eliminates the crystal oscillator start-up time, with a return to normal power within 3 milliseconds. again, to exit standby (i.e. to return to normal power consumption mode), the user must transmit a data mode command. the power during standby will be around 75 w. 2.11 power-up sequence and initialization care must be taken to assure that no pins are ever taken below the negative analog supply (va-) po- tential. the analog and digital supplies should be applied simultaneously to assure that the power-on reset circuit will automatically reset the adc when both supplies are at acceptable levels. commands should not be sent to the adc until a stable clock is present. if a 32.768 khz crystal is being used, it will take approximately 500 ms for the oscillator to stabilize after power has been ap- plied to the converter. if a cmos compatible source with no start-up delay is used, then the adc is immediately ready for a command. after a valid reset, the adc is placed into the com- mand state where it waits for a valid command to execute. once a valid conversion command has been received, conversions will begin and data can be read using the serial port. note: the cs5541 includes an on-chip power-on reset circuit to automatically reset the adc shortly after power-up. when power to the cs5541 is applied, the adc is held in a reset condition until the master clock has started and a counter-timer elapses (i.e. the counter-timer counts 490 mclk cycles to -140 -120 -100 -80 -60 -40 -20 0 0 20 40 60 80 100 120 frequency (hz) magnitude (db) 47 hz 63 hz figure 14. filter 1 response (mclk = 32.768 khz) -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (hz) magnitude (db) figure 15. filter 2 response (mclk = 32.768 khz)
cs5541 20 ds500pp1 make sure the oscillator is fully stable). in normal start-up conditions, this power on reset circuit should reset the chip when power is applied. if your application could experience abnormal power start-up conditions, it is recommended that the serial port reinitialization sequence, followed by a power save command, be performed to guarantee that the converter begins proper operation. 2.12 pcb layout the cs5541 should be placed entirely over an ana- log ground plane with the dgnd pin of the device connected to the analog ground plane. place the an- alog-digital plane split immediately adjacent to the digital portion of the chip see the cdb5540/41 data sheet for suggested lay- out details and applications note 18 for more de- tailed layout guidelines. applications engineering provides a free and con- fidential schematic review service.
cs5541 ds500pp1 21 3. pin descriptions clock generator osc1; osc2 - master clock. an inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock (powered relative to vd+) can be supplied into the osc1 pin to provide the master clock for the device. control pins and serial data i/o cs - chip select. when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. sdi - serial data input. sdi is the input pin of the serial input port. data will be input at a rate determined by sclk. sdo - serial data output. sdo is the serial data output. it will output a high impedance state if cs = 1. sclk - serial clock input. a clock signal on this pin determines the input/output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 vref+ vref- ain2+ ain2- dgnd vd+ sdo sclk cs ain1- ain1+ va+ va- osc2 osc1 sdi cs5541
cs5541 22 ds500pp1 measurement and reference inputs ain1+, ain1-, ain2+, ain2- - differential analog input. differential input pins into the device. vref+, vref- - voltage reference input. fully differential inputs which establish the voltage reference for the on-chip modulator. power supply connections va+ - positive analog power. positive analog supply voltage. va- - negative analog power. negative analog supply voltage. vd+ - positive digital power. positive digital supply voltage. dgnd - digital ground. digital ground.
cs5541 ds500pp1 23 4. specification definitions linearity error the deviation of a code from a straight line which connects the two end points of the a/d converter transfer function. one end point is located 1/2 lsb below the first code transition and the other end point is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code ? s width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs.
cs5541 24 ds500pp1 notes: 1. ? d ? and ? e1 ? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ? b ? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ? b ? dimension at maximum material condition. dambar intrusion shall not reduce dimension ? b ? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.005 0.010 0.05 0.13 0.25 a2 0.064 0.069 0.074 1.68 1.75 1.88 b 0.009 0.012 0.015 0.22 -- 0.38 2,3 d 0.232 0.244 0.256 5.90 6.20 6.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.0295 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 16l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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